1. Field of the Invention
The present invention relates to a semiconductor device having a capacitor constituting a dynamic random access memory (DRAM) cell wherein the capacity of the capacitor is increased by roughening a surface of the cylindrical storage node, and a method for producing such semiconductor device.
2. Discussion of Background
FIG. 6 is a cross-sectional view of a conventional semiconductor device as disclosed in JP-A-9-186297. FIG. 6 shows mainly the structure of a cylindrical capacitor in cross section, which constitutes a DRAM cell. In FIG. 6, reference numeral 101 designates a semiconductor substrate, numeral 101a designates a source/drain region as a transistor element formed in a surface region of the semiconductor substrate 101, numeral 102 designates a device isolation oxide layer formed on the surface of the semiconductor substrate 101, a numeral 103 designates a word line formed on the semiconductor substrate 101 through a gate insulating film, which constitutes a gate electrode of the transistor element, numeral 104 designates an interlayer insulating film formed on the transistor element, numeral 105a designates a cylindrical storage node formed in contact with a source/drain region 101a between adjacent source/drain regions, which is provided with a cylindrical portion extending upward at a position on the interlayer insulating film 104, numeral 106 designates a dielectric film formed on the cylindrical storage node 105a, and numeral 107 designates a cell plate laminated to cover an outer surface of the dielectric film 106. The cylindrical storage node 105a, the dielectric film 106 and the cell plate 107 constitute a cylindrical capacitor 108.
In the conventional semiconductor device shown in FIG. 6, the surface area of the storage node is increased by forming a plurality of pin holes 105aa in a cylindrical portion of the cylindrical storage node 105a.
A silicon layer constituting the cylindrical storage node 105a is formed by using a vapor-phase epitaxy method at a temperature which is higher than a temperature for forming an amorphous structure but lower than a temperature for forming a polycrystalline structure while an impurity gas is introduced therein.
However, since thus formed silicon layer has crystallized portions in it, that portions are easily etched earlier than the other portion. Under such circumstances, when an anisotropic etching is conducted to the silicon layer having locality crystallized portions, only the crystallized portions are selectively removed whereby pin holes 105aa are formed.
Another conventional technique for forming a roughened surface is disclosed in JP-A-7-74268. FIG. 7 shows the structure of a semiconductor device in cross section formed by such technique.
In the cross-sectional view showing mainly the structure of a cylindrical storage node 105b, the cylindrical storage node 105b has a cylindrical portion in which an inner wall and an upper surface of a bottom portion are roughened. Numeral 109 designates a bit line formed in contact with the other source/drain region 101a between the adjacent source/drain regions. Other reference numerals designate the same or corresponding part shown in FIG. 6. The reason why an outer wall of the cylindrical portion of the cylindrical storage node 105b is not roughened in the semiconductor device shown in FIG. 7, is to eliminate a disadvantage that when a heat treatment is conducted with use of a silane gas to obtain a roughened surface, spherical silicon grains having a uniform grain size are formed in the outer wall, and short circuit between adjacent storage nodes are caused. Further, there is another disadvantage that the formation of the silicon grains having a uniform grain size influences the formation of the dielectric film 106 and the cell plate 107 which are conducted subsequently.
In the conventional semiconductor device shown in FIG. 6, some of the pin holes 105aa penetrate from the outer wall to the inner wall of the cylindrical portion of the cylindrical storage node 105a. In this case, a sufficient physical strength can not be assured for the cylindrical storage node 105a, and there causes the destruction or the breakage of the cylindrical portion in subsequent processes.
In the conventional semiconductor device shown in FIG. 7, it was difficult to control the size of the silicon grains formed to obtain a roughened surface, and scattering of the silicon grain size was large whereby it was difficult to form a roughened surface in the cylindrical portion of the cylindrical storage node 105b.
It has been considered to control the scattering of the silicon grain size. With a demand of miniaturizing capacitor elements, the film thickness from the outer wall to the inner wall of the cylindrical portion has further been reduced. Under such circumstances, when both surfaces of the outer wall and the inner wall are to be roughened, silicon grains are entirely formed in the cylindrical portion whereby air gaps are resulted between adjacent silicon grains. In this case, the physical strength of the cylindrical portion can not be assured and there causes the destruction or the breakage of the cylindrical portion.
It has been considered to roughen both surfaces of the outer wall and the inner wall by controlling the grain size of the silicon grains to be mall. In this case, however, it is required to reduce the grain size of the silicon grains, and it is difficult to increase remarkably the surface area of the cylindrical portion.